发明授权
- 专利标题： Package design and method of manufacture for chip grid array
- 专利标题（中）： 芯片阵列的封装设计和制造方法
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申请号： US10236337申请日： 2002-09-06
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公开(公告)号： US06929981B2公开(公告)日： 2005-08-16
- 发明人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
- 申请人： Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
- 申请人地址： SG Singapore
- 专利权人： Advanpack Solutions PTE, Ltd.
- 当前专利权人： Advanpack Solutions PTE, Ltd.
- 当前专利权人地址： SG Singapore
- 代理商 George O. Saik; Stephen B. Ackerman; Rosemary L. S. Pike
- 主分类号： H01L23/31
- IPC分类号： H01L23/31 ; H01L23/36 ; H01L21/44
摘要：
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
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