发明授权
- 专利标题: Noninterfering multiply-MAC (multiply accumulate) circuit
- 专利标题(中): 非干扰乘法MAC(乘法累加)电路
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申请号: US09923461申请日: 2001-08-06
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公开(公告)号: US06957242B1公开(公告)日: 2005-10-18
- 发明人: Warren Snyder
- 申请人: Warren Snyder
- 申请人地址: US CA San Jose
- 专利权人: Cypress Semiconductor Corp.
- 当前专利权人: Cypress Semiconductor Corp.
- 当前专利权人地址: US CA San Jose
- 代理机构: Wagner, Murabito & Hao LLP
- 主分类号: G06F7/38
- IPC分类号: G06F7/38 ; G06F7/544 ; G06F7/57
摘要:
A noninterfering multiply-MAC (multiply accumulate) circuit is described. The circuit is operational to perform a MAC (multiply accumulate) operation and to perform a multiply operation without interfering with the accumulate value of the MAC operation. The circuit includes a first register, a second register, a multiplier circuit, and an accumulate circuit. The first register is addressable using either a primary first address or an alias first address. Moreover, the second register is addressable using either a primary second address or an alias second address. The multiplier circuit performs a multiply operation to generate a product value based on the data in the first and second registers after a write operation to either the first register or the second register. The accumulate circuit performs an accumulate operation to generate an accumulate value if either the alias first address or the alias second address is used in the write operation.
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