利索-全球专利检索

  1. 登录
  2. 注册
发明授权
US06959354B2 Effective bus utilization using multiple bus interface circuits and arbitration logic circuit 失效
有效总线利用率采用多总线接口电路和仲裁逻辑电路

Effective bus utilization using multiple bus interface circuits and arbitration logic circuit
摘要：
In one embodiment of the present invention, a bus controller is used in a multi-bus system having first and second buses. The bus controller includes first and second bus interface circuits, a processor interface circuit, and an arbitration logic circuit. The first and second bus interface circuits interface to the first and second buses, respectively. The first bus is accessible to a first processor. The processor interface circuit interfaces to a second processor. The arbitration logic circuit is coupled to the first and second bus interface circuits and the processor interface circuit to arbitrate access requests from the first and second processors.
摘要（中）：

在本发明的一个实施例中，总线控制器用于具有第一和第二总线的多总线系统中。 总线控制器包括第一和第二总线接口电路，处理器接口电路和仲裁逻辑电路。 第一和第二总线接口电路分别与第一和第二总线接口。 第一个总线可以访问第一个处理器。 处理器接口电路接口到第二处理器。 仲裁逻辑电路耦合到第一和第二总线接口电路和处理器接口电路以仲裁来自第一和第二处理器的访问请求。

公开/授权文献
信息查询
Espacenet
0/0