Invention Grant
US06963206B2 System and method of evaluating gate oxide integrity for semiconductor microchips
有权
评估半导体芯片的栅氧化物完整性的系统和方法
- Patent Title: System and method of evaluating gate oxide integrity for semiconductor microchips
- Patent Title (中): 评估半导体芯片的栅氧化物完整性的系统和方法
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Application No.: US10946558Application Date: 2004-09-21
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Publication No.: US06963206B2Publication Date: 2005-11-08
- Inventor: Deepak A. Ramappa
- Applicant: Deepak A. Ramappa
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Yingsheng Tung; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01N23/06
- IPC: G01N23/06 ; G01N27/60

Abstract:
The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a layer of gate oxide on the semiconductor wafer; a layer of polysilicon on the gate oxide; an electron beam microscope with adjustable energy levels, wherein the electron beam is directed at the semiconductor wafer; an electron beam inspection tool used to detect passive voltage contrasts within the gate oxide layer. The system may also include a measuring tool for measuring an electrical current level of the semiconductor substrate. The system may also include an electrical ground connected to the semiconductor wafer. The system may also include the energy levels vary from about 600 eV to 5000 eV.
Public/Granted literature
- US20050037525A1 System and method of evaluating gate oxide integrity for semiconductor microchips Public/Granted day:2005-02-17
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