发明授权
US06968306B1 Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model 失效
使用有效电容量度(ECM)信号延迟模型确定互连延迟的方法和系统

Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
摘要:
A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Ceff is computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Ceff is characterized by: Ceff=Cfj(1−e−T/τdj) where Cfj is the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and τdj is the resistance of the pi-model (Rdj) multiplied by Cfj. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.
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