发明授权
US06968306B1 Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
失效
使用有效电容量度(ECM)信号延迟模型确定互连延迟的方法和系统
- 专利标题: Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
- 专利标题(中): 使用有效电容量度(ECM)信号延迟模型确定互连延迟的方法和系统
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申请号: US09668320申请日: 2000-09-22
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公开(公告)号: US06968306B1公开(公告)日: 2005-11-22
- 发明人: Charles Jay Alpert , Anirudh Devgan , Chandramouli V. Kashyap
- 申请人: Charles Jay Alpert , Anirudh Devgan , Chandramouli V. Kashyap
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Dillon & Yudell LLP
- 代理商 Casimer K. Salys
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Ceff is computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Ceff is characterized by: Ceff=Cfj(1−e−T/τdj) where Cfj is the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and τdj is the resistance of the pi-model (Rdj) multiplied by Cfj. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.
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