A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.