发明授权
US07009878B2 Data reprogramming/retrieval circuit for temporarily storing programmed/retrieved data for caching and multilevel logical functions in an EEPROM
有权
数据重新编程/检索电路,用于临时存储用于EEPROM中的缓存和多级逻辑功能的编程/检索数据
- 专利标题: Data reprogramming/retrieval circuit for temporarily storing programmed/retrieved data for caching and multilevel logical functions in an EEPROM
- 专利标题(中): 数据重新编程/检索电路,用于临时存储用于EEPROM中的缓存和多级逻辑功能的编程/检索数据
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申请号: US10664977申请日: 2003-09-22
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公开(公告)号: US07009878B2公开(公告)日: 2006-03-07
- 发明人: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
- 申请人: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
- 申请人地址: JP Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Kawasaki
- 代理机构: Banner & Witcoff, Ltd.
- 优先权: JP2000-63798 20000308; JP2000-323199 20001023
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
公开/授权文献
- US20040057310A1 Non-volatile semiconductor memory 公开/授权日:2004-03-25
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