发明授权
US07017103B2 Device and method for Viterbi equalization with metric increments calculated in advance
失效
维特比均衡的装置和方法,其预先计算出的公制增量
- 专利标题: Device and method for Viterbi equalization with metric increments calculated in advance
- 专利标题(中): 维特比均衡的装置和方法,其预先计算出的公制增量
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申请号: US10336556申请日: 2003-01-03
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公开(公告)号: US07017103B2公开(公告)日: 2006-03-21
- 发明人: Peter Bohnhoff , Burkhard Becker , Bin Yang
- 申请人: Peter Bohnhoff , Burkhard Becker , Bin Yang
- 申请人地址: DE Munich
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE Munich
- 代理商 Laurence A. Greenberg; Werner H. Stemer; Ralph E. Locher
- 优先权: DE10032237 20000703
- 主分类号: H03M13/03
- IPC分类号: H03M13/03
摘要:
A Viterbi equalizer for equalization of a data signal transmitted via a channel that is subject to interference has at least one add-compare-select unit (ACS), which carries out an ACS operation for each channel state in a time step k. Furthermore, the equalizer has a unit for calculating metric increments in advance and for storing the metric increments. The calculation unit calculates in advance the metric increments relating to all the transitions from a state which can be predetermined in the time step k to the states which can be reached by the transitions in the time step k+1. The metric increments are retained in an output memory such that they can be called up for utilization in the ACS unit.
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