发明授权
- 专利标题: Timing attack resistant cryptographic system
- 专利标题(中): 定时攻击加密系统
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申请号: US09761700申请日: 2001-01-18
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公开(公告)号: US07020281B2公开(公告)日: 2006-03-28
- 发明人: Ashok Vadekar , Robert J. Lambert
- 申请人: Ashok Vadekar , Robert J. Lambert
- 申请人地址: CA Mississauga
- 专利权人: Certicom Corp.
- 当前专利权人: Certicom Corp.
- 当前专利权人地址: CA Mississauga
- 代理商 John R. S. Orange; Santosh K. Chari; Sean X. Zhang
- 优先权: CA2243761 19980721
- 主分类号: H04L9/00
- IPC分类号: H04L9/00
摘要:
A method for determining a result of a group operation performed an integral number of times on a selected element of the group, the method comprises the steps of representing the integral number as a binary vector; initializing an intermediate element to the group identity element; selecting successive bits, beginning with a left most bit, of the vector. For each of the selected bits; performing the group operation on the intermediate element to derive a new intermediate element; replacing the intermediate element with the new intermediate element; performing the group operation on the intermediate element and an element, selected from the group consisting of: the group element if the selected bit is a one; and an inverse element of the group element if the selected bit is a zero; replacing the intermediate element with the new intermediate element. In a final step, performing the group operation on the intermediate value and the inverse element if the last selected bit is a zero; and replacing the intermediate element therewith, to obtain the result, whereby each of the bits of the integral is processed with substantially equal operations thereby minimizing timing attacks on the cryptographic system.
公开/授权文献
- US20010033655A1 Timing attack resistant cryptographic system 公开/授权日:2001-10-25
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