发明授权
US07027548B1 Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings
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使用这些设置可实现宽范围，高精度延迟锁定环和延迟锁定环实现的延迟设置
- 专利标题： Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings
- 专利标题（中）： 使用这些设置可实现宽范围，高精度延迟锁定环和延迟锁定环实现的延迟设置
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申请号： US09873016申请日： 2001-05-30
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公开(公告)号： US07027548B1公开(公告)日： 2006-04-11
- 发明人: Chaitanya Palusa , Abhijit Ray
- 申请人： Chaitanya Palusa , Abhijit Ray
- 申请人地址： US CA Santa Clara
- 专利权人： Alliance Semiconductor Corporation
- 当前专利权人： Alliance Semiconductor Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Stallman & Pollock LLP
- 主分类号： H03D3/24
- IPC分类号： H03D3/24
摘要：
A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.
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