Invention Grant
- Patent Title: Self aligned damascene gate
- Patent Title (中): 自对准镶嵌门
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Application No.: US10699887Application Date: 2003-11-04
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Publication No.: US07029958B2Publication Date: 2006-04-18
- Inventor: Cyrus E. Tabery , Shibly S. Ahmed , Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
- Applicant: Cyrus E. Tabery , Shibly S. Ahmed , Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity Snyder, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
Public/Granted literature
- US20050104091A1 Self aligned damascene gate Public/Granted day:2005-05-19
Information query
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