A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.