发明授权
- 专利标题： Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
- 专利标题（中）： 具有优化的浅结几何形状的半导体器件及其制造方法
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申请号： US10835121申请日： 2004-04-29
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公开(公告)号： US07033879B2公开(公告)日： 2006-04-25
- 发明人: Brian E. Hornung , Xin Zhang , Lance S. Robertson , Srinivasan Chakravarthi , Beriannan Chidambaram
- 申请人： Brian E. Hornung , Xin Zhang , Lance S. Robertson , Srinivasan Chakravarthi , Beriannan Chidambaram
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Rose Alyssa Keagy; W. James Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L21/336
摘要：
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).