The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit 51. A first address for test is applied to an address terminal 21, whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.