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US07042094B2 Via structure for semiconductor chip 失效
半导体芯片通孔结构

Via structure for semiconductor chip
摘要:
A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.
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