In an electronic ballast the output d.c. voltage (U) of a PFC intermediate circuit (3) is to be regulated. The intermediate circuit (3) has a clocked switch (S) which is controlled by a regulation circuit (7). The regulation circuit (7) includes two counters (Z1, Z2). The counter (Z1) has a greater number of count stages than the counter (Z2). The counter (Z1) is counted upwards or downwards in dependence upon the regulation difference. The counter (Z2) is repeatedly counted only in one direction and for example reset by a reset signal. By comparing the counts of corresponding count stages of the two counters (Z1) and (Z2) in a comparator, the switch on time (ton) for the clock switch (S) is determined.