- 专利标题: Packaging substrates for integrated circuits and soldering methods
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申请号: US10739707申请日: 2003-12-17
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公开(公告)号: US07060601B2公开(公告)日: 2006-06-13
- 发明人: Sergey Savastiouk , Patrick B. Halahan , Sam Kao
- 申请人: Sergey Savastiouk , Patrick B. Halahan , Sam Kao
- 申请人地址: US CA Sunnyvale
- 专利权人: Tru-Si Technologies, Inc.
- 当前专利权人: Tru-Si Technologies, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: MacPherson Kwok Chen & Heid LLP
- 代理商 Michael Shenker
- 主分类号: H01L21/20
- IPC分类号: H01L21/20
摘要:
A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The dies (124) are attached to the interposer after the attachment of the interposer to the BT substrate. In sequential soldering operations, the solder hierarchy is maintained by dissolving some material (e.g. copper) in the solder during soldering to raise the solder's melting temperature. For example, all of the solders may initially have the same melting temperature, but each solder's melting temperature is increased during soldering to prevent the solder from melting in the subsequent soldering operations.
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