发明授权
US07071044B1 Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS
失效
使用常规CMOS制作门体电流测试结构并直接提取物理栅极长度的方法
- 专利标题: Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS
- 专利标题(中): 使用常规CMOS制作门体电流测试结构并直接提取物理栅极长度的方法
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申请号: US10838229申请日: 2004-05-05
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公开(公告)号: US07071044B1公开(公告)日: 2006-07-04
- 发明人: Srinath Krishnan , William George En
- 申请人: Srinath Krishnan , William George En
- 申请人地址: US CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of the transistor. Gate insulator and polysilicon layers are formed, and the polysilicon is implanted with dopant, to a concentration level expected in the transistor gate. After gate patterning, the methodology involves forming sidewall spacers and implanting dopant into the active device well, to form regions in the test structure corresponding to the transistor source and drain. Although the concentrations mimic those in the transistor source and drain, these test structure regions are doped with opposite type dopant material. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for measurement of gate length.