发明授权
US07072816B1 Method and system for providing hierarchical self-checking in ASIC simulation
失效
在ASIC仿真中提供分层自检的方法和系统
- 专利标题： Method and system for providing hierarchical self-checking in ASIC simulation
- 专利标题（中）： 在ASIC仿真中提供分层自检的方法和系统
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申请号： US09409940申请日： 1999-09-30
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公开(公告)号： US07072816B1公开(公告)日： 2006-07-04
- 发明人: Bryan Keith Bullis , Raj Kumar Singh , Foster Beaver White
- 申请人： Bryan Keith Bullis , Raj Kumar Singh , Foster Beaver White
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Sawyer Law Group LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.
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