A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.