发明授权
- 专利标题: Speed and memory optimized interleaving
- 专利标题(中): 速度和内存优化交错
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申请号: US10526519申请日: 2002-09-09
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公开(公告)号: US07091889B2公开(公告)日: 2006-08-15
- 发明人: Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
- 申请人: Ralf Kukla , Stefan Schütz , Georg Spörlein , Gerd Mörsberger
- 申请人地址: SE Stockholm
- 专利权人: Telefonaktiebolaget LM Ericsson (publ)
- 当前专利权人: Telefonaktiebolaget LM Ericsson (publ)
- 当前专利权人地址: SE Stockholm
- 代理商 Roger Burleigh
- 国际申请: PCT/EP02/10073 WO 20020909
- 国际公布: WO2004/025839 WO 20040325
- 主分类号: H03M7/00
- IPC分类号: H03M7/00
摘要:
This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.
公开/授权文献
- US20050248473A1 Speed and memory optimised interleaving 公开/授权日:2005-11-10
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