- 专利标题: Bit line reference circuits for binary and multiple-bit-per-cell memories
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申请号: US11151863申请日: 2005-06-13
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公开(公告)号: US07099188B1公开(公告)日: 2006-08-29
- 发明人: Sau Ching Wong
- 申请人: Sau Ching Wong
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 代理机构: Volentine Francos & Whitt
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; G11C16/06 ; G11C7/06 ; G11C5/14 ; G11C7/00 ; G11C7/02
摘要:
Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.
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