发明授权
US07101746B2 Method to lower work function of gate electrode through Ge implantation
有权
通过Ge注入来降低栅电极的功函数的方法
- 专利标题: Method to lower work function of gate electrode through Ge implantation
- 专利标题(中): 通过Ge注入来降低栅电极的功函数的方法
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申请号: US10701963申请日: 2003-11-05
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公开(公告)号: US07101746B2公开(公告)日: 2006-09-05
- 发明人: Tze Ho Simon Chan , Mousumi Bhat , Jeffrey Chee
- 申请人: Tze Ho Simon Chan , Mousumi Bhat , Jeffrey Chee
- 申请人地址: SG Singapore
- 专利权人: Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人: Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Saile Ackerman LLC
- 代理商 Stephen B. Ackerman
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L21/336
摘要:
A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.
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