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US07101776B2 Method of fabricating MOS transistor using total gate silicidation process
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使用全栅极硅化工艺制造MOS晶体管的方法
- 专利标题: Method of fabricating MOS transistor using total gate silicidation process
- 专利标题(中): 使用全栅极硅化工艺制造MOS晶体管的方法
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申请号: US10806301申请日: 2004-03-22
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公开(公告)号: US07101776B2公开(公告)日: 2006-09-05
- 发明人: Jae-Yoon Yoo , Hwa-Sung Rhee , Ho Lee , Seung-Hwan Lee
- 申请人: Jae-Yoon Yoo , Hwa-Sung Rhee , Ho Lee , Seung-Hwan Lee
- 申请人地址: KR
- 专利权人: Samsung Electronics, Co., Ltd.
- 当前专利权人: Samsung Electronics, Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Mills & Onello LLP
- 优先权: KR10-2003-0046983 20030710
- 主分类号: H01L21/44
- IPC分类号: H01L21/44 ; H01L21/3205 ; H01L21/4763
摘要:
There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.
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