An oscillator delay stage is described. The oscillator delay stage includes at least one differential input; a pair of single ended inverters for each differential input; and, a differential output. With respect to the pair of single ended inverters for each differential input, each pair of single ended inverters further include for their corresponding differential input: i) a first single ended inverter whose input is coupled to a + input of the corresponding differential input; and, ii) a second single ended inverter whose input is coupled to a − input of the corresponding differential input. With respect to the differential output, the differential input further includes: i) a + output that is coupled to each said second single ended inverter output; ii) a − output that is coupled to each said first single ended inverter output.