- 专利标题: Test device, test system and method for testing a memory circuit
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申请号: US10452485申请日: 2003-06-02
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公开(公告)号: US07107501B2公开(公告)日: 2006-09-12
- 发明人: Carsten Ohlhoff , Peter Beer
- 申请人: Carsten Ohlhoff , Peter Beer
- 申请人地址: DE Munich
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE Munich
- 代理商 Laurence A. Greenberg; Werner H. Stemer; Ralph E. Locher
- 优先权: DE10224184 20020531; DE10226584 20020614
- 主分类号: G11C29/00
- IPC分类号: G11C29/00 ; G06F12/00
摘要:
A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.