- 专利标题: Methods of fabricating a semiconductor device having a metal gate pattern
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申请号: US10665122申请日: 2003-09-22
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公开(公告)号: US07109104B2公开(公告)日: 2006-09-19
- 发明人: Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
- 申请人: Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
- 申请人地址: KR Gyeonggi-do
- 专利权人: Samsung Electronics Ltd., Co.
- 当前专利权人: Samsung Electronics Ltd., Co.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: Harness, Dickey & Pierce
- 优先权: KR10-2002-0057456 20020919
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L21/3205 ; H01L21/4763
摘要:
A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
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