Invention Grant
- Patent Title: Quad flat no lead (QFN) grid array package
- Patent Title (中): 四边形无铅(QFN)格栅阵列封装
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Application No.: US10728413Application Date: 2003-12-05
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Publication No.: US07109572B2Publication Date: 2006-09-19
- Inventor: Setho Sing Fee , Lim Thiam Chye
- Applicant: Setho Sing Fee , Lim Thiam Chye
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Priority: SG200104675 20010806
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01R9/00

Abstract:
A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.
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