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发明授权
US07109749B2 Programmable logic devices providing reduced power consumption 有权
提供降低功耗的可编程逻辑器件

Programmable logic devices providing reduced power consumption
摘要：
A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.
摘要（中）：

一种可编程逻辑器件，用于为顺序逻辑和数据存储功能提供功率消耗降低，包括至少一个电路装置，其可配置为在电路时钟选定的一个或两个边缘上工作的双边沿触发触发器。

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