发明授权
- 专利标题： Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word
- 专利标题（中）： 减少指令集计算机架构，在数据字中多次从指令的立即字段重复位值
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申请号： US10675759申请日： 2003-09-29
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公开(公告)号： US07114055B1公开(公告)日： 2006-09-26
- 发明人: Michael A. Baxter
- 申请人： Michael A. Baxter
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Pablo Meles
- 代理商 LeRoy D. Maunu
- 主分类号： G06F15/76
- IPC分类号： G06F15/76
摘要：
A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.
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