Invention Grant
- Patent Title: Stacked chip package having upper chip provided with trenches and method of manufacturing the same
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Application No.: US10962591Application Date: 2004-10-13
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Publication No.: US07115483B2Publication Date: 2006-10-03
- Inventor: Yong Hwan Kwon , Se Yong Oh , Sa Yoon Kang
- Applicant: Yong Hwan Kwon , Se Yong Oh , Sa Yoon Kang
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR2001-38103 20010629
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/44 ; H01L21/30 ; H01L23/02
Abstract:
A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.
Public/Granted literature
- US20050051882A1 Stacked chip package having upper chip provided with trenches and method of manufacturing the same Public/Granted day:2005-03-10
Information query
IPC分类:
