A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.