DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a controllable active-current generator (7, 8, 9, 10) for providing power to the sense amplifiers and pre-charge circuits (15) for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device (1) and an assigned switching time; a controllable standby-current generator (6) for providing power to the sense amplifiers and pre-charge circuits (15) after the switching time; a control circuit (11) for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator (7, 8, 9, 10) and the standby-current generator (6); wherein the control circuit (11) is adapted to control the time for switching the respective power generator (6, 7, 8, 9, 10) to the sense amplifiers and to the pre-charge circuits (15) subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits (15).