Invention Grant
US07124270B2 Transceiver with latency alignment circuitry 有权
具有延迟对准电路的收发器

Transceiver with latency alignment circuitry
Abstract:
A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.
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