- 专利标题: Clock frequency detect with programmable jitter tolerance
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申请号: US11000439申请日: 2004-11-30
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公开(公告)号: US07129757B2公开(公告)日: 2006-10-31
- 发明人: Charles Porter Geer , Robert Allen Shearer
- 申请人: Charles Porter Geer , Robert Allen Shearer
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Robert R. Williams
- 主分类号: G01R25/00
- IPC分类号: G01R25/00
摘要:
An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.
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