发明授权
US07129861B2 Method for implementing a fractional sample rate converter (F-SRC) and corresponding converter architecture
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实现分数采样率转换器(F-SRC)和相应转换器架构的方法
- 专利标题: Method for implementing a fractional sample rate converter (F-SRC) and corresponding converter architecture
- 专利标题(中): 实现分数采样率转换器(F-SRC)和相应转换器架构的方法
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申请号: US11065199申请日: 2005-02-24
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公开(公告)号: US07129861B2公开(公告)日: 2006-10-31
- 发明人: Vito Antonio Avantaggiati
- 申请人: Vito Antonio Avantaggiati
- 申请人地址: IT Vimercate
- 专利权人: Accent S.p.A.
- 当前专利权人: Accent S.p.A.
- 当前专利权人地址: IT Vimercate
- 代理机构: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- 代理商 Lisa K. Jorgenson
- 优先权: EP04425110 20040224
- 主分类号: H03M7/00
- IPC分类号: H03M7/00
摘要:
An up-sampled data stream, upsampled times a factor P, is generated by the input block providing signal samples having a frequency rate, while an intermediate data stream is generated by a Rate Adapting Stage providing signal samples adapted to an intermediate frequency rate. An output data stream is delivered by a final low pass filter, and includes M signal samples having a desired output sample frequency rate (fOUT=M/Ts). The method provides generation of a provisional stream in the Rate Adapting Stage, wherein this provisional stream is affected by aliases falling within the output Nyquist band [−fOUT/2, fOUT/2], although being adapted to the output frequency rate by a direct insertion of zero samples into the processed stream when L M. Then these aliases are suppressed in the Rate Adapting Stage by weighting the provisional stream via a set of weights.
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