- 专利标题: Method for fabricating semiconductor package having conductive bumps on chip
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申请号: US11338056申请日: 2006-01-23
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公开(公告)号: US07132312B2公开(公告)日: 2006-11-07
- 发明人: Chien-Ping Huang , Cheng-Hsu Hsiao
- 申请人: Chien-Ping Huang , Cheng-Hsu Hsiao
- 申请人地址: TW
- 专利权人: Siliconware Precision Industrial Co., Ltd.
- 当前专利权人: Siliconware Precision Industrial Co., Ltd.
- 当前专利权人地址: TW
- 代理机构: Edwards Angell Palmer & Dodge LLP
- 代理商 Peter F. Corless; Steven M. Jensen
- 优先权: TW92115508A 20030609
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
A semiconductor package having conductive bumps on a chip and a fabrication method thereof are provided. A plurality of the conductive bumps are deposited respectively on bond pads of the chip. An encapsulation body encapsulates the chip and conductive bumps while exposing ends of the conductive bumps. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings for exposing predetermined portions of the conductive traces. The exposed portions of the conductive traces are connected to a plurality of solder balls respectively. The conductive bumps on the bond pads of the chip allow easy positional recognition of the bond pads, making the conductive traces well electrically connected to the bond pads through the conductive bumps and assuring the quality and reliability of the semiconductor package.
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