发明授权
- 专利标题： Method for packaging integrated circuit chips
- 专利标题（中）： 集成电路芯片封装方法
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申请号： US10823877申请日： 2004-04-14
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公开(公告)号： US07135779B2公开(公告)日： 2006-11-14
- 发明人: James Anderson , Gershon Akerling
- 申请人： James Anderson , Gershon Akerling
- 申请人地址： US CA Los Angeles
- 专利权人： Northrop Grumman Corporation
- 当前专利权人： Northrop Grumman Corporation
- 当前专利权人地址： US CA Los Angeles
- 代理机构： Warner, Hoffmann, Miller & LaLone, P.C.
- 代理商 John A. Miller
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
A method for packaging integrated circuits in a wafer format that eliminates wire bonds. A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias. A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits.
公开/授权文献
- US20040248342A1 Method for packaging integrated circuit chips 公开/授权日：2004-12-09
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