A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.