Invention Grant
US07142586B2 Robust delay estimation architecture 有权
稳健的延迟估计架构

Robust delay estimation architecture
Abstract:
In a robust delay estimator system and method, an average PDP buffer serves as a source of reliable control information to other stages of the delay estimator. The PDP output from every path searcher and tuning finger pass is accumulated in the average PDP buffer, which maintains average PDP estimates for the whole allowable delay spread range. The current (i.e., instantaneous) PDP estimate is then added to the average PDP using an exponential averaging method. The average PDP buffer stores the current PDP estimate and the average PDP estimate, as well as timing and other types of information regarding the estimates. The information in the average PDP provides the necessary information for, and is used to control the operation of, all the individual sub-stages of the delay estimation process.
Public/Granted literature
Information query
Patent Agency Ranking
0/0