Invention Grant
- Patent Title: Robust delay estimation architecture
- Patent Title (中): 稳健的延迟估计架构
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Application No.: US10246873Application Date: 2002-09-18
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Publication No.: US07142586B2Publication Date: 2006-11-28
- Inventor: Andres Reial
- Applicant: Andres Reial
- Applicant Address: SE Stockholm
- Assignee: Telefonaktiebolaget LM Ericsson (publ)
- Current Assignee: Telefonaktiebolaget LM Ericsson (publ)
- Current Assignee Address: SE Stockholm
- Main IPC: H04B1/707
- IPC: H04B1/707

Abstract:
In a robust delay estimator system and method, an average PDP buffer serves as a source of reliable control information to other stages of the delay estimator. The PDP output from every path searcher and tuning finger pass is accumulated in the average PDP buffer, which maintains average PDP estimates for the whole allowable delay spread range. The current (i.e., instantaneous) PDP estimate is then added to the average PDP using an exponential averaging method. The average PDP buffer stores the current PDP estimate and the average PDP estimate, as well as timing and other types of information regarding the estimates. The information in the average PDP provides the necessary information for, and is used to control the operation of, all the individual sub-stages of the delay estimation process.
Public/Granted literature
- US20040052304A1 Robust delay estimation architecture Public/Granted day:2004-03-18
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