Invention Grant
US07144786B2 Technique for forming a transistor having raised drain and source regions with a reduced number of process steps
有权
用于形成具有减少的工艺步骤数量的具有升高的漏极和源极区域的晶体管的技术
- Patent Title: Technique for forming a transistor having raised drain and source regions with a reduced number of process steps
- Patent Title (中): 用于形成具有减少的工艺步骤数量的具有升高的漏极和源极区域的晶体管的技术
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Application No.: US10891996Application Date: 2004-07-15
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Publication No.: US07144786B2Publication Date: 2006-12-05
- Inventor: Ralf van Bentum , Scott Luning , Thorsten Kammler
- Applicant: Ralf van Bentum , Scott Luning , Thorsten Kammler
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE10351006 20031031
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.
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