发明授权
US07145250B2 LSI package, LSI element testing method, and semiconductor device manufacturing method
有权
LSI封装,LSI元件测试方法和半导体器件制造方法
- 专利标题: LSI package, LSI element testing method, and semiconductor device manufacturing method
- 专利标题(中): LSI封装,LSI元件测试方法和半导体器件制造方法
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申请号: US11113063申请日: 2005-04-25
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公开(公告)号: US07145250B2公开(公告)日: 2006-12-05
- 发明人: Shigeyuki Maruyama , Toru Nishino , Kazuhiro Tashiro
- 申请人: Shigeyuki Maruyama , Toru Nishino , Kazuhiro Tashiro
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Westerman, Hattori, Daniels & Adrian, LLP.
- 主分类号: H01L29/40
- IPC分类号: H01L29/40 ; H01L23/48 ; H01L23/52
摘要:
An LSI package comprises an LSI element and a wiring board. The plurality of pin terminals of the LSI element each includes a first conductive layer and a second conductive layer superposed on the first conductive layer. The plurality of pin terminals of the wiring board each includes a third conductive layer joined to the second conductive layer, and the wiring board further comprises outer joining terminals. The first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer. The LSI element is tested using the outer joining terminals of the wiring board. The second conductive layer and third conductive layer are joined to attain a metallic bond through aggregation derived from pressure, and are reliably brought into electrical contact with each other for a test. After the test is completed, the terminals of the LSI element are peeled off from the terminals of the wiring board. At this time, the second conductive layer is transferred to the third conductive layer, and the first conductive layer is left intact in each of the terminals of the LSI element. The LSI element is then mounted on another wiring board.