发明授权
US07148543B2 Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions
失效
组合体积和SOI区域并与多个隔离区域分开的半导体芯片
- 专利标题： Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions
- 专利标题（中）： 组合体积和SOI区域并与多个隔离区域分开的半导体芯片
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申请号： US10828337申请日： 2004-04-21
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公开(公告)号： US07148543B2公开(公告)日： 2006-12-12
- 发明人: Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
- 申请人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2001-298533 20010927
- 主分类号： H01L27/01
- IPC分类号： H01L27/01 ; H01L27/12 ; H01L29/00 ; H01L29/04 ; H01L29/06
摘要：
A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
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