Invention Grant
US07149992B2 Method for faster timing closure and better quality of results in IC physical design
有权
更快的时序关闭方法和更好的IC物理设计质量
- Patent Title: Method for faster timing closure and better quality of results in IC physical design
- Patent Title (中): 更快的时序关闭方法和更好的IC物理设计质量
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Application No.: US10669496Application Date: 2003-09-23
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Publication No.: US07149992B2Publication Date: 2006-12-12
- Inventor: Xin Chang , Penny Wang , Shuming Chuang
- Applicant: Xin Chang , Penny Wang , Shuming Chuang
- Applicant Address: TW
- Assignee: Via Technologies, Inc.
- Current Assignee: Via Technologies, Inc.
- Current Assignee Address: TW
- Agency: Dechert LLP
- Agent Anthony B. Diepenbrock, III
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A selective IPO procedure based on the concept of a “timing violation potential” prioritizes the components and nets in a critical path. User input criteria is used to select the components or nets (or both) which have the larger “timing violation potential;” only those components and nets are then operated on. After a selective IPO step, the total number of critical paths is reduced, as well as the worst negative slacks (WNS) of the critical path compared to the traditional IPO method.
Public/Granted literature
- US20040111686A1 Method for faster timing closure and better quality of results in IC physical design Public/Granted day:2004-06-10
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