Invention Grant
US07151001B2 Fabrication method of self-aligned ferroelectric gate transistor using buffer layer of high etching selectivity
有权
使用高蚀刻选择性的缓冲层的自对准铁电栅极晶体管的制造方法
- Patent Title: Fabrication method of self-aligned ferroelectric gate transistor using buffer layer of high etching selectivity
- Patent Title (中): 使用高蚀刻选择性的缓冲层的自对准铁电栅极晶体管的制造方法
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Application No.: US10922949Application Date: 2004-08-23
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Publication No.: US07151001B2Publication Date: 2006-12-19
- Inventor: Yong-Tae Kim , Seong-Il Kim , Chun-Keun Kim , Sun-Il Shim
- Applicant: Yong-Tae Kim , Seong-Il Kim , Chun-Keun Kim , Sun-Il Shim
- Applicant Address: KR Seoul
- Assignee: Korea Institute of Science and Technology
- Current Assignee: Korea Institute of Science and Technology
- Current Assignee Address: KR Seoul
- Agency: McDermott Will & Emery LLP
- Priority: KR10-2003-0059188 20030826
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.
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