发明授权
- 专利标题: MOS transistor and method of manufacture
- 专利标题(中): MOS晶体管及其制造方法
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申请号: US10762788申请日: 2004-01-22
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公开(公告)号: US07151059B2公开(公告)日: 2006-12-19
- 发明人: Samir Chaudhry , Sidhartha Sen , Sundar Srinivasan Chetlur , Richard William Gregor , Pradip Kumar Roy
- 申请人: Samir Chaudhry , Sidhartha Sen , Sundar Srinivasan Chetlur , Richard William Gregor , Pradip Kumar Roy
- 申请人地址: US PA Allentown
- 专利权人: Agere Systems Inc.
- 当前专利权人: Agere Systems Inc.
- 当前专利权人地址: US PA Allentown
- 主分类号: H01L21/31
- IPC分类号: H01L21/31
摘要:
A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
公开/授权文献
- US20040150014A1 MOS transistor and method of manufacture 公开/授权日:2004-08-05
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