发明授权
US07154724B2 Output buffer ESD protection using parasitic SCR protection circuit for CMOS VLSI integrated circuits
有权
输出缓冲器ESD保护，使用CMOS VLSI集成电路的寄生SCR保护电路
- 专利标题： Output buffer ESD protection using parasitic SCR protection circuit for CMOS VLSI integrated circuits
- 专利标题（中）： 输出缓冲器ESD保护，使用CMOS VLSI集成电路的寄生SCR保护电路
-
申请号： US10812378申请日： 2004-03-29
-
公开(公告)号： US07154724B2公开(公告)日： 2006-12-26
- 发明人: Yi-Hsun Wu , Jian-Hsing Lee
- 申请人： Yi-Hsun Wu , Jian-Hsing Lee
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Duane Morris, LLP
- 主分类号： H02H9/04
- IPC分类号： H02H9/04 ; H01L23/62
摘要：
An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer, and a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground, wherein a voltage drop across the diode string increases the SCR gate holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.
公开/授权文献
信息查询
