Invention Grant
- Patent Title: Method of controlling a bit line for a content addressable memory
- Patent Title (中): 控制内容可寻址存储器的位线的方法
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Application No.: US11101873Application Date: 2005-04-09
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Publication No.: US07154764B2Publication Date: 2006-12-26
- Inventor: Bindiganavale S. Nataraj
- Applicant: Bindiganavale S. Nataraj
- Applicant Address: US CA Mountain View
- Assignee: NetLogic Microsystems, Inc.
- Current Assignee: NetLogic Microsystems, Inc.
- Current Assignee Address: US CA Mountain View
- Agent William L Paradice, III
- Main IPC: G11C15/00
- IPC: G11C15/00

Abstract:
A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM) Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.
Public/Granted literature
- US20050174822A1 Bit line control circuit for a content addressable memory Public/Granted day:2005-08-11
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