Invention Grant
US07167686B2 Wireless communications transceiver: transmitter using a harmonic rejection mixer and an RF output offset phase-locked loop in a two-step up-conversion architecture and receiver using direct conversion architecture
有权
无线通信收发器:使用谐波抑制混频器的发射机和使用直接转换架构的两级上转换架构和接收机中的RF输出偏移锁相环
- Patent Title: Wireless communications transceiver: transmitter using a harmonic rejection mixer and an RF output offset phase-locked loop in a two-step up-conversion architecture and receiver using direct conversion architecture
- Patent Title (中): 无线通信收发器:使用谐波抑制混频器的发射机和使用直接转换架构的两级上转换架构和接收机中的RF输出偏移锁相环
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Application No.: US10350407Application Date: 2003-01-24
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Publication No.: US07167686B2Publication Date: 2007-01-23
- Inventor: Puay-Hoe Andrew See , James Jaffee , Steven Mollenkopf , Sandor Szabo
- Applicant: Puay-Hoe Andrew See , James Jaffee , Steven Mollenkopf , Sandor Szabo
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agent Philip R. Wadsworth; Charles D. Brown; Kenyon S. Jenckes
- Main IPC: H04B1/40
- IPC: H04B1/40

Abstract:
A wireless transceiver includes a transmitter having a harmonic rejection mixer and an RF output phase-locked loop in a two step up-conversion architecture, and a direct conversion receiver. The transmitter includes a local oscillator for producing a signal at a multiple of an intermediate frequency, a quadrature modulator harmonic rejection mixer responsive to the signal at the multiple of the intermediate frequency for modulating in-phase and quadrature-phase base-band signals to produce an intermediate frequency signal, a filter responsive to the intermediate frequency signal for producing a filtered intermediate frequency signal, and an RF output offset phase-locked loop responsive to the filtered intermediate frequency signal and the signal at the multiple of the intermediate frequency for producing an RF transmission signal. The harmonic rejection mixer reduces filtering requirements to facilitate a high level of circuit integration. The local oscillator may use a integer or fractional-N phase-locked loop.
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