发明授权
- 专利标题: Wafer level semiconductor package with build-up layer and method for fabricating the same
- 专利标题(中): 具有积层的晶片级半导体封装及其制造方法
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申请号: US10846460申请日: 2004-05-14
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公开(公告)号: US07170152B2公开(公告)日: 2007-01-30
- 发明人: Chien-Ping Huang , Cheng-Hsu Hsiao , Chih-Ming Huang
- 申请人: Chien-Ping Huang , Cheng-Hsu Hsiao , Chih-Ming Huang
- 申请人地址: TW
- 专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人地址: TW
- 代理机构: Edwards Angell Palmer & Dodge LLP
- 代理商 Peter F. Corless; Steven M. Jensen
- 优先权: TW93106438A 20040311
- 主分类号: H01L23/02
- IPC分类号: H01L23/02
摘要:
A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.